Need AVR Help

[Adam]

Our micro-process teacher gave us a few questions to answer.
I only have 3 left that I can't find the answers on the internet to.
Can someone help me out.


1. What is the status register used for?

2. How many milliampere can an AVR-processor port handle when draining or sourcing?

3. In what categories are instructions to an AVR-processor divided?

[Kingroudy]

1- i didn't study AVR, but i can answer the first question since i have experience in PIC processors, the status register has the size of any other register, and where every bit represent an ALU status (or memory bank if it exists in AVR)
some of the bits are
C: carry bit, set to one when the ALU operation generates a carry
DC: digit carry.. same concept
Z: the Zero bit, if the result of an ALU operation is zero, this bit will be set.
(the Z bit is nothing but a NAND Gate)
OV bit: set to 1 when there is an overflow
N bit: set to 1 when a negative value is generated.

i was talking about the PIC, but the concept is the same. i suggest you download the datasheet of the AVR you are working on, and i will try to help you if you have a question.

[Markouz]

I had a project last semester in which we had to build a robot based on sensors. It was all programmed using AVR, and answering question number 2) it can handle 1 microAmpere (check out the datasheet of Atmega8 or PIC microcontrollers..)

Enjoy!

[Google]

Answering the left question, the third one. The AVR instructions are divided into:

Arithmetic:
ADD Rd, Rr
ADC Rd, Rr
ADIW Rd+1:Rd, K6
SUB Rd, Rr
SUBI Rd, K8
SBC Rd, Rr
SBCI Rd, K8
SBIW Rd+1:Rd, K6
INC Rd
DEC Rd
AND Rd, Rr
ANDI Rd, K8
OR Rd, Rr
ORI Rd, K8
EOR Rd, Rr

COM Rd
NEG Rd
CP Rd, Rr
CPC Rd, Rr
CPI Rd, K8
SWAP Rd
LSR Rd
ROR Rd
ASR Rd

MUL Rd, Rr
MULS Rd, Rr
MULSU Rd, Rr
FMUL Rd, Rr
FMULS Rd, Rr
FMULSU Rd, Rr


Bit and others:
BSET s
BCLR s
SBI A, b
CBI A, b
BST Rd, b
BLD Rd, b
NOP
BREAK
SLEEP
WDR

Transfer:
MOV Rd, Rr
MOVW Rd+1:Rd, Rr+1:Rr
IN Rd, A
OUT A, Rr
PUSH Rr
POP Rr
LDI Rd, K8
LDS Rd, K16
LD Rd, X
LD Rd, -X
LD Rd, X+
LDD Rd, Y+K6
LD Rd, -Y
LD Rd, Y+
LDD Rd, Z+K6
LD Rd, -Z
LD Rd, Z+
STS K16, Rr
ST X, Rr
ST -X, Rr
ST X+, Rr
STD Y+K6, Rr
ST -Y, Rr
ST Y+, Rr
STD Z+K6, Rr
ST -Z, Rr
ST Z+, Rr
LPM
LPM Rd, Z
LPM Rd, Z+
ELPM
ELPM Rd, Z
ELPM Rd, Z+
SPM

Jump:
RJMP K12
IJMP
EIJMP
JMP K22

Branch:
CPSE Rd, Rr
SBRC Rr, b
SBRS Rr, b
SBIC A, b
SBIS A, b
BRBC s, K7
BRBS s, K

Call:
RCALL K12
ICALL
EICALL
CALL K22
RET
RETI

As for the status register. It is also called "Flag register". It contains the current state of the processor. I think that all the architectures have the same BASIC flags. On the x86 architecture, the flags are:

FLAGS
0- Carry flag
1- Reserved
2- Parity flag
3- Reserved
4- Adjust flag
5- Reserved
6- Zero flag
7- Sign flag
8- Trap flag
9- Interrupt enable flag
10- Direction flag
11- Overflow flag
12,13- I/O Privilege level
14- Nested task flag
15- Reserved

EFLAGS
16- Resume flag
17- Virtual 8086 mode
18- Alignment check
19- Virtual interrupt flag
20- Virtual interrupt pending
21- Identification
22- Reserved
23- Reserved
24- Reserved
25- Reserved
26- Reserved
27- Reserved
28- Reserved
29- Reserved
30- Reserved
31- Reserved

RFLAGS
32-63- Reserved

Notice the 16-32-64 bit.

[Adam]

Thanks, you guys are lifesavers
Only one month left in school and I've got way too much work stacked up that needs to be finished, glad I don't have to spend an other hour searching Google for these answers (maybe I should've paid attention in class )